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SI9167
New Product
Vishay Siliconix
600-mA Synchronous Buck Converter for 2-Cell Li+ Cellular Phones
FEATURES
D D D D D D Voltage Mode Control 5-V to 10-V Input Voltage Range Fully Integrated 600-mA MOSFET Switches Synchronous Rectifier Switch Synchronizable, Constant-Frequency PWM Mode (up to 2 MHz) Programmable PWM/PSM Control - Up to 600-mA Output Current in PWM with 950-mA Quiescent Current - Up to 150-mA Output Current in PSM with 200-mA Quiescent Current D Low Dropout Operation at Low VIN - VOUT D Integrated UVLO, POR and OTP D Integrated Soft-Start D Shutdown Current <1 mA D Power Good Comparator
DESCRIPTION
The SI9167 provides a fully integrated synchronous buck converter solution for the latest 2-cell Lithium Ion battery cellular phones. Capable of delivering up to 600mA of output current, the SI9167 provides ample power for various Baseband circuits as well as for some PAs. Combined with its integrated low gate charge high-frequency MOSFETs and internal synchronous rectifier, the SI9167 delivers efficiency up to 95%. The programmable pulse-skipping mode maintains high efficiency even during the standby mode to increase overall battery life and talk time. In order to extract the last ounce of power from battery, SI9167 is designed with 100% duty cycle capability for both PSM and PWM operating modes. With 100% duty cycle, SI9167 operates like a saturated linear regulator to deliver the highest potential output voltage. The SI9167 is available in TSSOP-20 pin package. In order to satisfy the stringent ambient temperature requirements, SI9167 is specified over the industrial temperature range of -25_C to 85_C.
The SI9167 combines the 2-MHz switching frequency with fully integrated high-frequency MOSFETs to deliver the smallest and most efficient converter available today. The 2-MHz switching frequency reduces the inductor height to a new level of less than 2 mm and minimizes the output capacitance requirement to less than 10 mF, with only 10-mV peak-to-peak output ripple.
FUNCTIONAL BLOCK DIAGRAM
VIN (5-10 V)
1.3 V X 10 V SMPS
VOUT (1.3 X 10 V)
1.3 V Voltage Reference PWR_GD INPUT PWR_GD OUTPUT SD Power_Good Comparator Shutdown Control
VREF (1.3 V)
Document Number: 70898 S-63920--Rev. C, 23-Aug-99
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SI9167
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to AGND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 V PWM/PSM, SYNC, CLK, SD,AIN, AO, VREF, ROSC, COMP, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VS + 0.3 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ."0.3 V Voltages Referenced to PGND VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V COIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 V to VIN + 0.4 V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 20-Pin TSSOP (Q Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.56 W Thermal Impedance (QJA) 20-Pin TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 12.5 mW/_C above 25_C.
New Product
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to GND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 10 V Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 kHz to 2 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 kW to 300 kW VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 to 10 V PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD VREF Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 mF Voltages Referenced to PGND VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 V to 10 V
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage VREF Current VREF PSRR VREF IREF PSRR IREF = 0 VDD = 7.2 V, IREF = 0, 25_C 1.2675 1.280 1.3 1.3 -0.5 60 1.3325 1.320 V mA dB
Limits
-25_C to 85_C
Symbol
5 V v VDD v 10 V, VIN = VDD
Mina
Typb
Maxa
Unit
UVLO
Under Voltage Lockout (Turn-On) Hysteresis 4.25 4.5 0.2 4.75 V
Soft-Start Time
SS Time tSS 10 ms
SD, SYNC, PWM/PSM
Logic High Logic Low 2.4 0.8 V
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Document Number: 70898 S-63920--Rev. C, 23-Aug-99
SI9167
New Product
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Oscillator
Maximum Frequency Accuracy Maximum Duty Cycle (Non LDO Mode) SYNC Range SYNC Low Pulse Width SYNC High Pulse Width SYNC tr, tf tr, tf (10% to 90%) DMAX FSYNC/FOSC FMAX 1% External Resistor FSW = 2 MHZ FSYNC v 2 MHz 1.2 50 50 50 ns -20 80 1.5 2 20 % MHz
Vishay Siliconix
Limits
-25_C to 85_C
Symbol
5 V v VDD v 10 V, VIN = VDD
Mina
Typb
Maxa
Unit
Error Amplifier
Input Regulation Range Input Bias Current Open Loop Voltage Gain Power Supply Rejection Unity Gain BW Output Current (Source) Output Current (Sink) VFB IBIAS AVOL PSRR BW IEA VFB = 1.05 V VFB = 1.55 V 1 VFB = 1.4 V 1.260 -1 50 60 60 2 -2 2 -0.5 1.340 1 V mA dB MHz mA
PSM Modulator
Inductor Peak Current IPEAK VDD = 7.2 V, VOUT = 3.3 V 500 mA
Output Capability
PWM Mode Outputc PSM Mode Outputc rDS(ON) High Side rDS(ON) Low Side IOUT rDS(ON-P) rDS(ON-N) VDD = VIN = 7.2 V, VOUT = 3.3 V VDD = VIN = 7.2 V 600 150 300 300 mA
mW
Over Temperature Protection
Trip Point Hysteresis 165 25 _C
Supply Current
PWM Mode PSM Mode Shutdown Mode VDD = VIN = 7.2 V FOSC = 1 6 MH 1.6 MHz 950 200 1350 350 1 mA A
Power Good Comparator
POKIN Trip Level POKIN Input Current POKIN Hysteresis POK Low Voltage POK High Leakage Current ISINK(POK) = 1 mA 0.001 Rising VPOKIN 1.270 -20 30 50 0.4 1 1.300 1.330 20 V nA mV V mA
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. c. Guaranteed by design and characterization, not subject to production testing.
Document Number: 70898 S-63920--Rev. C, 23-Aug-99
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SI9167
Vishay Siliconix
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
VREF vs. VDD
1.320 1.315 1.310 V REF (V) V REF (V) 1.305 1.300 1.295 1.290 1.285 1.28 4 6 8 VDD (V) 10 12 1.278 1.308 1.328
VREF vs. Temperature
1.318
1.298
1.288
1.268 -50
-25
0
25
50
75
100
Ambient Temperature (_C)
Frequency vs. Temperature
2.2 VDD = 7.2 V ROSC = 25 kW 10000
Frequency vs. ROSC
2.1 Frequency (MHz)
2.0
Frequency (kHz)
1000
1.9
1.8
1.7 -50
0
50
100
150
100 10
100 ROSC (kW)
1000
Ambient Temperature (_C)
Max Duty Cycle vs. Frequency
98 VIN = 7.2 V 96 90 % Max Duty Cycle 94 Efficiency (%) 92 90 88 60 86 84 400 50 600 800 1000 1200 1400 1600 1800 2000 Frequency (kHz) 10 80 100
Efficiency, VO = 3.6 V
PWM-VIN = 7.2 V PSM-VIN = 5 V PSM-VIN = 7.2 V PWM-VIN = 5 V
PWM-VIN = 8.4 V
70
PSM-VIN = 8.4 V
100 Load Current (mA)
1000
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Document Number: 70898 S-63920--Rev. C, 23-Aug-99
SI9167
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Vishay Siliconix
PWM Supply Current vs. VDD
1400 300
PSM Supply Current vs. VDD
1200
250
1000 I DD ( (mA) I DD ( (mA) 200
800
150
600 100
400
200 4 6 8 VDD (V) 10 12
50 4 6 8 VDD (V) 10 12
TYPICAL WAVEFORMS
VIN = 7.2 V, VO = 3.6 V, Step IO = 0 to 150 mA Step Load Slew Rate = 1 A/msec Ch1: VOUT (50 mV/div) Ch2: IOUT (100 mA/div)
FIGURE 1. Transient Response PSM Mode
Document Number: 70898 S-63920--Rev. C, 23-Aug-99
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SI9167
Vishay Siliconix
TYPICAL WAVEFORMS
New Product
VIN = 7.2 V, VO = 3.6 V, Step IO = 0 to 600 mA Step Load Slew Rate = 1 A/msec Ch1: VOUT (100 mV/div) Ch2: IOUT (500 mA/div)
FIGURE 2. Transient Response PWM Mode
VIN = 7.2 V, VO = 3.6 V, IO = 150 mA Ch1: VOUT (50 mV/div) Ch3: Coil (5 V/div)
FIGURE 3. PSM Output Ripple
VIN = 7.2 V, VO = 3.6 V, IO = 600 mA Ch1: VOUT (10 mV/div) Ch3: Coil (5 V/div)
FIGURE 4. PWM Output Ripple
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Document Number: 70898 S-63920--Rev. C, 23-Aug-99
SI9167
New Product
TYPICAL WAVEFORMS
Vishay Siliconix
VIN = 7.2 V, VO = 3.6 V, IO = 150 mA Ch1: VOUT (200 mV/div) Ch2: Inductor Current (500 mA/div) Ch3: PWM/PSM (High PWM, Low PSM)
FIGURE 5. PSM-PWM-PSM Transition
PIN CONFIGURATION
TSSOP-20
SD PWM/PSM VIN VIN POK SYNC CLK GND VREF FB 1 2 3 4 5 6 7 8 9 10 Top View 20 19 18 17 16 15 14 13 12 11 COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP
ORDERING INFORMATION
Part Number
SI9167BQ-T1
Temperature Range
-25 to 85_C
Package
Tape and Reel
SI9167BQ
Eval Kit
SI9167DB
Temperature Range
-25 to 85_C
Board Type
Surface Mount
PIN DESCRIPTION
Pin Number
1 2 3, 4 5 6 7 8 9 10 11 12 13 14 15 16, 18 17, 19, 20 Document Number: 70898 S-63920--Rev. C, 23-Aug-99
Name
SD PWM/PSM VIN POK SYNC CLK GND VREF FB COMP ROSC VDD VO POKIN PGND COIL Logic high = PWM mode, logic low = PSM mode.
Function
Shuts down the IC completely and decreases current consumed by the IC to <1 mA. Input node for buck converter as well as input supply voltage for the internal MOSFET gate drive voltage. Power_good comparator output, It sinks current when VPOKIN <1.3 V, high Impedance state during disable. Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. Oscillator output Analog ground 1.3-V reference. Bypassed with 0.1-mF capacitor. Output voltage feedback Error amplifier output for external compensation network External resistor to set the switching frequency Supply voltage for the control circuit Direct output voltage sense Power_good comparator input Power ground Inductor connection node www.siliconix.com S FaxBack 408-970-5600
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SI9167
Vishay Siliconix
BLOCK DIAGRAM
VDD Positive Supply SD VIN
New Product
Reference Threshold Generator VREF VO FB COMP
1.3 V
Soft-Start Timer
UVLO
POR System Monitor
Bias Generator
OTP
PWM Modulator 1.0 V Ramp Oscillator COSC PWMIN 0.5 V PWMIN PWM/PFM Select PSMIN PSMIN PSM Modulator - + Drivers COIL
SYNC CLK ROSC
POKIN POK PWM/PSM
Negative Return and Substrate GND PGND
FIGURE 1.
DETAIL OPERATIONAL DESCRIPTION
UVLO The UVLO circuit prevents the internal MOSFET switches and oscillator circuit from turning on, when the input voltage is too low to regulate output voltage. Failing to do this could unintentionally lock up the system. The typical turn on threshold is 4.5 V with a turn off hysteresis of 0.2 V. circuit slowly regulates the output voltage from 0 V to its intended level. This soft-start phase typically lasts for 3 ms. Note that the SI9167 always soft-starts in the PWM mode regardless of the voltage level on the PWM/PSM pin.
Shutdown STARTUP Once the input voltage is above the turn on threshold, and with no other shutdown condition detected, the system enters a POR (power on reset) phase, which lasts about 1 ms. During this POR phase, most of the circuits are activated, except for the power switches. After the POR phase, an internal soft-start
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The SI9167 is designed to conserve as much battery life as possible by decreasing current consumption of the IC during normal operation as well as in the shutdown mode. With logic low level on the SD pin, current consumption of the SI9167 is decreased to less than 1 mA by shutting off most of the circuits. The logic high enables the converter and starts up as described in "Start-Up" section above.
Document Number: 70898 S-63920--Rev. C, 23-Aug-99
8
SI9167
New Product
DETAIL OPERATIONAL DESCRIPTION
Over Temperature Protection The SI9167 is designed with an over temperature protection circuit to prevent the MOSFET switches from overheating. If the temperature reaches 165_C, internal soft-start capacitor is discharged, shutting down the output stage. The converter remains in the disabled mode until the temperature in the IC decreases below 140_C. PWM Mode With PWM/PSM pin pulled logic high, SI9167 operates in constant frequency (PWM) mode. The converter regulates the output voltage by modulating the MOSFET switch duty cycle. Switching harmonics generated by fixed-frequency operation are consistent and easy to filter. The switching frequency is programmed by the ROSC value as shown by the oscillator curve. In the PWM mode, the synchronous switch is always enabled, which permits the converter to run in continuous current mode, even when the output current reaches 0 A. In continuous current mode, the transfer function of the converter remains constant, providing fast transient response. If the converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be ten times longer than if the converter remains in continuous current mode. This transient response time advantage can significantly decrease the size of the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltage regulation. The SI9167 can operate at 100% duty cycle, when it operates like a saturated linear regulator. This allows the system designers to extract out the maximum stored energy from the battery. As input voltage drops close to output regulation level, the converter will approach maximum switching duty cycle, about 80%, at full switching frequency. As input voltage further decreases, the converter will enter 100% duty cycle mode. This instantaneous jump in duty cycle is due to BBM time and the internal propagation delays. In order to maintain regulation, the converter might change its duty cycle back and forth from 100% to maximum switching duty cycle during this input voltage range. If the input voltage drops further, the converter will remain at 100% duty cycle. If the input voltage increases to a point where it requires less than maximum duty cycle, about 80%, the converter will resume normal PWM operation. Pulse Skipping Mode Gate charge losses of MOSFETs can be the dominant power dissipation during light load (i.e. <10 mA) if the converter is switching at high frequency. With PWM/PSM pin pulled logic low, the SI9167 operates in PSM mode. During this mode, the converter switching frequency is lower than PWM switching frequency in order to achieve high power efficiency at light load. By building up inductor current to a fixed level during each cycle, the converter regulates the output voltage with variable switching frequency, depending on the operating condition.
Document Number: 70898 S-63920--Rev. C, 23-Aug-99
Vishay Siliconix
During PSM mode, a comparator detects the output voltage out of regulation and sets up a charging cycle. Depending upon the input to output voltage difference, the high-side MOSFET is on for certain amount of time and off for a shorter duration. This on-off cycle continues until the output voltage rises above the target level. the comparator detects this condition and idles the converter until the output falls under the converter output regulation level. Here, the comparator initializes another charge cycle. During the idle time, when both switches are off, the load is supplied by the output capacitor. When the input voltage approaches the programmed output voltage the converter operates as a saturated linear regulator. If the input voltage is lower than the programmed output voltage then the converter operates in a 100% duty cycle mode such that the output voltage will closely follow the input voltage. REF The reference voltage of the SI9167 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The reference voltage output is bypassed by 0.1-mF capacitor. Error Amplifier In order to establish high-speed system response, the SI9167 is designed with 2-MHz error amplifier to generate the widest converter bandwidth and 3.5-V/ms slew rate for fast large signal response. Oscillator The oscillator is designed to operate up to 2-MHz minimal. The 2-MHz operating frequency allows the converter to minimize the inductor and capacitor size, improve the power density of the converter. Attaching a resistor to ROSC pin easily programs the switching frequency. See oscillator frequency versus Rosc curve to select the proper values for desired operating frequency. The tolerance on the operating frequency is "20% with 1% tolerance resistor. Synchronization The synchronization with external clock is easily accomplished by connecting the external clock into the SYNC pin. Logic high to low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. CLK Output During PWM mode, CLK pin provides oscillator signal for users to synchronize other converters in order to set the harmonics to avoid IF bands in wireless applications. This is accomplished by connecting CLK of the master to Sync of the slave.
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SI9167
Vishay Siliconix
DETAIL OPERATIONAL DESCRIPTION
Break-Before-Make Timing A proper BBM time is essential in order to prevent shoot-through current and maintain high efficiency. The break-before-make time is set internally at 20 to 40 ns @ VDD = 7.2 V. After one switch (either high-side or low-side) is turned off, 20- to 40-ns BBM time is set before the other switch turns on. The maximum and minimum controllable duty cycle is primarily limited by the BBM time. Since the BBM time is fixed, maximum controllable duty cycle will vary depending on the switching frequency. Typically, the higher the PWM switching frequency, the lower the maximum duty cycle and the higher the minimum duty cycle. Output MOSFET Stage The high and low-side switches are integrated to provide optimum performance and to minimize the overall converter size. Both high and low-side switches are designed to handle up to 600 mA of continuous current. The MOSFET switches were designed to minimize the gate charge loss as well as the conduction loss. For high frequency operation, switching losses can exceed conduction loss, if the switches are designed incorrectly. Under full load, efficiency of up to 95% is accomplished with 7.2-V battery voltage (3.3-V output voltage).
New Product
Power Good Comparator The SI9167 has an uncommitted power good comparator. This comparator has its negative input connected directly to 1.3-V reference and has a typical hysteresis of 50 mV at room temperature. Its output is an open-drain n-channel MOSFET capable of sinking 1 mA. This output is open circuit in the shutdown mode.
STANDARD APPLICATION
1 C1 10 mF 16 V
+VIN 5 - 10 V
PGND
2
R1* 51 W C1 0.1 mF
SI9167
ENABLE/DISABLE PWM/PSM R9* 51 kW 1 2 3 4 5 6 7 8 1.3 V C3 0.1 mF 9 10 SD PWM/PSM VIN VIN POK SYNC CLK GND VREF FB COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP R3 8.2 kW C5 1000 pF C4 56 pF 20 MBRO520T1 19 18 17 16 15 14 13 12 11 R2 75 kW D1
3.6 V @ 600 mA L1 4.7 mH IHLP2525 C1 10 mF 16 V C9 0.1 mF 7 VOUT
8
PGND
R7 105 kW
R8 64 kW
C6 0.1 mF R4 200 W C7 330 pF R6 12.4 kW R5 22 kW
STAR GND CON
* Optional
FIGURE 2. Typical Application Circuit--Buck
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